The Intel Xeon Phi co-processor

The Intel has finally disclosed additional details of Xeon Phi co-processor.The Xeon Phi is massive chip about 5 billion transistors using Intel's most advanced 22nm process technology with 3D tri-gate transistors. A maximunm of 62 cores can fit on a single die. Each core is a simple in order x86 CPU with a 512-bit SIMD unit. The core can handle four thread simultaneously. Nehalem, Sandy and Ivy bridge also use SMT, but those cores uses SMT mostly to make better use of their ample execution resources. In case of Xeon Phi core, the 4 threads are mostly a way to hide memory latency. In the best case, two threads will execute in parallel. Each of these cores is a 64-bit x86 core. However, only 2% of the core logic is spent on x86 logic. The SIMD unit does not support MMX, SSE or AVX the Xeon Phi has its own vector format. All the cores are connected together with a bi-directional ring, similar to what's used in the Xeon E7 and the Sandy Bridge EP CPUs. Eight memory channels (512-bit interface) support up to 8GB of RAM, and PCIe logic is on chip.