Ceva targets basestations with FP cores

Ceva Inc., is driving its DSP technology toward wireless base stations and other high end products with a set of new floating point and multicore features. Ceva has
added capability to handle up to 32 floating point operations per clock cycle to its CEVA-CX vector processor unit. The feature enables handling jobs such as MIMO antenna
processing including 4 by 4 configurations for 802.11as WiFi at up to 1.7Gbits/second, Ceva claims.
              It added a range of multicore features for symmetric and asymmetric clusters running at up to a GHz including support for cache coherency in DSP and mixed DSP
and MPU clusters. Ceva's approach builds on ARM AXI4 interconnect protocol and AMBA 4 ACE cache coherency extensions. The company also provided enhancements
aimed at simplify programming multicore clusters.